1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device and a method of using the same, and particularly to a non-volatile semiconductor memory device capable of storing at least three different data in each memory cell and to a method of writing or reading data in or from that memory device.
2. Description of the Related Art
The prior art documents disclosing the non-volatile semiconductor memory device, which the present invention relates to, are listed as follows;
Document 1: A 16 Kb Electrically Erasable Nonvolatile Memory, 1980, IEEE, ISSCC, Dig. Tech. Pap., pp 152-153, 271, 1980.
Document 2: Analysis and Modeling of Floating-Gate EEPROM Cells, IEEE Trans., Electron Devices, 1986, June, ED-33, No.6, pp 835-844.
Document 3: Semiconductor MOS Memory and Method of Using the Same, Nikkan Kogyo Newspaper Co., 1990, pp 96-101.
Document 4: A Novel Cell Structure Suitable For A 3 Volt Operation, Sector Erase Flash Memory, IEDM 92, pp.599-602 (1992).
Document 5: Flash EEPROM Memory Systems Having Multistate Storage Cells, U.S. Pat. No. 5,043,940 (1991).
A non-volatile semiconductor memory device in which the recorded data is not lost even if the power supply is turned off (this is called PROM) has already been developed and practically used since the early 1970's. In addition, another non-volatile semiconductor memory device (hereinafter, referred to as EEPROM) which is electrically erasable has been practically used since the 1980's, as described in the document 1. In the write operation of a memory cell of the EEPROM, the memory cell of a transistor-structure having a floating gate is charged with electrons and discharged through a thin insulating oxide film according to the Fowler-Nordheim tunneling effect, so that the threshold voltage of the transistor can be controlled (see documents 1 and 2). The threshold value of the memory cell is increased by injecting electrons into the floating gate and decreased by discharging electrons and injecting holes.
For example, FIG. 2 of document 3 shows the functional block diagram of this EEPROM. FIG. 13 in this application is a circuit block diagram of the conventional EEPROM which is given for comparison with the present invention. In FIG. 13, there are shown 144 memory cells of 4 columns and 36 rows, in which nine bits in data are simultaneously read or programmed. In order to make programming, erasing or reading for the 144 selective memory cells, it includes, as illustrated, decoder circuits, multiplexers, address buffers, a chip control circuit, a high-voltage generation/control circuit, a programming circuit, a sense circuit, data input buffer and data output buffer.
In FIG. 13, there are also shown address input terminals 501, 502, 503 and 504 which are used for inputting the address data of a memory cell selected by column and row lines. Input control terminals 505, 506 and 507 are used for inputting control signals for controlling the operation mode of the EEPROM; that is, the input terminal 505 is used for inputting a chip selection signal, the input terminal 506 for inputting an output selection signal, and the input terminal 507 for inputting a write signal. There are shown input/output terminals 508 through 516 from which the stored data of the selected memory cells are read out in the read mode and to which the data to be stored in the memory cells are supplied in the write mode.
Address buffers 517 through 520 function to buffer and output the address data and to reduce the consumption current in the input portion in response to a power-down signal. Another conventional technique is known (see document 3) in which the address buffer has an additional function of latching the address data in response to a latch signal in the write mode.
A chip control circuit 521 is responsive to the control signals at the control input terminals 505, 506 and 507 to select the read mode, write mode, power-down mode (or standby mode) and output nonselection mode. The chip control circuit 521 also includes the function by which the erase mode and program mode are automatically terminated in accordance with the internal timer. The write mode is further divided into two different modes, the erase mode and the program mode. In the erase mode, the selected memory cell or memory cells of a memory block are brought into the erased state in order to write other data into the memory cell or cells. The erased state of the memory cell means that the threshold value of the memory cell is higher (or lower) than the gate voltage in the read operation. In the program mode, the selected memory cell is in the programmed state in accordance with the input data. The programmed state means that the threshold value of the memory cell is lower (or higher) than the gate voltage in the read operation. When the memory cell is rewritten with other data, the erase mode is selected so that the memory cell is made into the erase state, and then into the programmed state in accordance with the input data. In other words, the write mode includes the erase mode and the program mode.
A column decoder 522 decodes the outputs from the address buffers 517 and 518, and applies a high (H) voltage only to the column line (the word line) of the selected memory cell, and a low voltage to the column lines of the non-selected cells. The high voltage upon selection is about the power supply voltage in the read mode, but becomes high in the write mode.
A row decoder 523 decodes the outputs from the address buffers, and it supplies a high voltage to the row line (bit line) of a selected memory cell and a low voltage to the row lines of the non-selected memory cells through multiplexers 529 and 537.
A high-voltage generation/control circuit 524 has a circuit for increasing the power supply voltage supplied to the EEPROM in the write mode to generate a high voltage of about 10 through 25 V (referred to as charge pump circuit), and a control circuit for supplying a desired high voltage to respective circuits of the EEPROM in accordance with the erase mode or program mode.
A sense circuit 525 detects and amplifies the voltage value or current value on a data line 614 to which the data of the selected memory cell is transmitted in the read mode through the row line and multiplexers 529 through 537, and the amplified voltage or current value is outputted to a data output buffer 527.
A program circuit 526 receives a signal of program mode and the high voltage and supplies a high or low voltage depending on the input data to the data line 614. In this case, the conventional EEPROM can produce only a high voltage or low voltage (normally 0 V) signal.
The data output buffer 527 receives the data from the sense circuit 525 and supplies it to the output terminal in the read mode. Also it has a function of inhibiting the output in the power-down mode or the output non-selection mode.
A data input buffer 528 buffers the input data from the input/output terminal 516 and supplies it to the program circuit 526 in the write mode. Another data input buffer is known which has a function of latching the input data in the write mode in response to the latch signal.
Each of the multiplexers 529 through 537 connects the selected row line to a data line 614 or 629 through 636 in accordance with the signal from the row decoder 523. The voltage from the row decoder 523 is about that of the power supply voltage in the read mode and a high voltage in the write mode.
There are shown column lines 617,618, 619 and 620, and row lines 637 through 672. There are also shown memory sense program lines 625, 626, 627 and 628, and memory cells 542 through 557. Each memory cell includes one select transistor and one memory transistor, and has the same structure and connection as shown in FIGS. 2 and 3 of document 1. In the memory cell shown in FIG. 3 of document 1, the column line is connected to the gate of the select transistor, the row line to the drain of the select transistor, and the memory sense program line to the gate of the memory transistor.
In FIG. 13, the upper and right side terminals of each of the blocks 542 through 557 indicating the respective memory cells are connected to the gate and drain of the select transistor, respectively, and the lower and left side terminals thereof to the gate and source of the memory transistor, respectively.
Each of MARY 1 through MARY 3 has three memory cell arrays MARY 01 through MARY 03 of the same structure and connection. Each memory cell array is formed of memory cells of four rows and four columns. The upper side terminals of the memory cells of respective columns are connected to the column lines 617 through 620, the lower side terminals of the memory cells of respective columns to memory sense program lines 625 through 628, and the left side terminals of all the memory cells to a memory ground line 610.
A circuit block DI01 includes the program circuit, the sense circuit, the data input buffer and the data output buffer. The data line to these circuits is represented by reference numeral 614, and the input/output terminal to these circuits is represented by reference numeral 516. Shown at 615 is the output from the data input buffer 528 and also the input to the program circuit 526, and at 616 is the output from the sense circuit 525 and also the input to the data output buffer 527. The circuit blocks DI02 . . . DI09 have the same construction as the circuit block DI01. The data lines to those blocks are represented by reference numerals 629 through 636, respectively, and the input/output terminals to those blocks by reference numerals 515 through 508, respectively.
Shown at 601 is the output from the address buffer 517 and the input to the column decoder 522, at 602 is the output from the address buffer 518 and the input to the column decoder 522, and at 603 is the output from the address buffer 519 and the input to the row decoder 523. Shown at 604 is the output from the address buffer 520 and the input to the row decoder 523, and at 621 through 624 are the outputs from the row decoder 523 and the inputs to the multiplexers 529 through 537.
Shown as 605 is the power down signal from the chip control circuit 521. This signal is supplied to the address buffers 517 through 520. Shown as 606 is a read enable signal for activating or inactivating the sense circuits 525 of the blocks DI01 through DI09. Shown at 607 is the program signal which, in the program mode, activates the program circuits 526 of the blocks DI01 through DI09 and causes the high-voltage generation/control circuit 524 to generate high voltages on high voltage lines 608 and 609 and a memory sense line 611 to be kept at 0 V. Shown at 673 is the erase signal for causing the high-voltage generation/control circuit 524 to generate the high voltage at the outputs 608 and 611 in the erase mode. Reference numeral 612 denotes a data input enable signal for activating the data input buffers 528 of the blocks DI01 through DI09 in the write mode, and 613 is a data output enable signal for activating the data output buffers 527 of the blocks DI01 through DI09 in the read mode.
Reference numeral 608 is a first high voltage signal which is supplied from the high voltage generation/control circuit 524 to the column decoder 522 and the row decoder 523 in the write mode. Shown as 611 is a memory sense signal which is at 0 V in the program mode, at the high voltage in the erase mode and at an intermediate voltage between 0 V to the power supply voltage in the reading mode. Shown as 609 is a second high voltage signal which is at the high voltage in the program mode.
Circuit blocks 538 through 541 connect the memory sense signal 611 from the high voltage generation/control circuit 524 to one of the memory sense program lines 625 to 628 corresponding to one column selected by the signals on the column lines 617 through 620.
The write operation and read operation of the conventional EEPROM will be described briefly. In the read operation, the control signals applied to the control input terminals 505, 506 and 507 are rendered into the read mode, and the selected address data are applied to the address input terminals 501, 502, 503 and 504. The input address data are buffered by the address buffers 517 through 520, and decoded by the column decoder 522 and row decoder 523.
A selected one of the four output signal lines of the column decoder 522 which are respectively connected to the column lines 617 through 620 is at a high voltage (normally about the power supply voltage), and the other three signal lines are at a low voltage. In addition, one row line is selected from the row lines 637 through 640 by the outputs 621 through 624 from the row decoder 523 and the multiplexer 529. Only the selected one row line is electrically connected to the data line 614 through a low impedance.
Similarly, the row lines selected, respectively, by the outputs 621 through 624 of the row decoder 523 and multiplexer 530, the outputs 621 through 624 and multiplexer 531, . . . , the outputs 621 through 624 and multiplexer 537 are electrically connected to the data lines 629 through 636 through a low impedance. At this time, a threshold detection voltage of, for example, 2 through 4 V corresponding to the detected threshold value of the memory cell is supplied to the memory sense line 611 and fed through the memory sense program line selecting circuits 538 through 541 only to the selected one of the memory sense program lines. The memory ground line 610 is in the grounded state.
The voltage from the corresponding sense circuit (for example, 525 in DI01) is supplied to the row line of the selected memory cell. When the threshold voltage of the memory cell is lower than the threshold detection voltage, the memory cell transistor is turned on and thus a current flows from the row line to the memory ground line 610. When the threshold voltage of the memory cell is higher than the threshold detection voltage, the selected memory cell transistor is turned off and thus no current flows from the row line to the memory ground line 610. The voltage on the row line is set by the sense circuit, and the current to the row line in the read mode is supplied from the sense circuit. The sense circuit detects and amplifies this current, thereby outputting the stored data in the memory cell on the line 616 in, for example, DI01 as a binary value of a high or low voltage, which is fed through the data output buffer 527 to the outside. If the threshold value of the memory cell is as high as 6 V, a high voltage is produced at the input/output terminal 516. If the threshold value of the memory cell is as low as 0 V, a low voltage is produced at the input/output terminal. The sense circuit and data input buffer in DI02 through DI09 have the same functions as those in DI01.
In the write mode operation, the data in the memory cell is erased first. In this prior art, the data erasing is normally effected at a time or the memory cells in one column line, but may be effected on the memory cells for one byte or block. Although the erase mode in the prior art is effected by the control input to the input terminals 505, 506, 507, it is also possible to effect the erase mode by the input data to the data input buffer 528 in addition to the control input. In the erase mode, the column line of the memory cell is selected by the address data from the address input terminals 501, 502. The high voltage line 608 is kept at a high voltage and the column line of the selected memory cell is at a high voltage and 0 V is fed to the column lines of the other memory cells. In addition, the memory sense line 611 is at a high voltage and the memory sense program line of the column line of the selected memory cell is at a high voltage by the memory sense program line selecting circuits 538 through 541.
The sense circuit and program circuit (for example, 525, 526 in DI01) are not activated in the erasing mode, and the data line 614, 629 through 636 are at 0 V or in the floating state. The memory ground line 610 is grounded in the erasing mode. Thus, a high voltage (for example, 20 V) is applied to the gate of the memory cell of the selected column line and the drain and source are grounded. At this time, the Fowler-Nordheim tunnel phenomenon occurs, causing electrons to be injected from the drain into the floating gate so that the threshold value of the memory cell transistor becomes high (for example, 5 through 8 V).
When programming the erased memory device, the device is rendered to the program mode and the address of the memory cell to be programmed is inputted to the address input terminals 501, 502, 503, 504. In the program mode, the high voltage line 608 is set at a high voltage, the memory sense line 611 is at 0 V, and the high voltage line 609 is set at a high voltage. Also the memory ground line 610 is in the floating state. The column decoder 522, the row decoder 523, the program circuits 519, 523 and the data input buffers 520 in DI01 through DI09 are activated, while the sense circuits and the data output buffers are inactivated. In other words, when a low voltage is supplied as input data to the input/output terminal 516, the program circuit 526 produces a high voltage (for example, 20 V) on the data line 614, and when a high voltage is supplied to the input/output terminal 516, it produces 0 V on the data line 614. When the data line 614 is at a high voltage, the selected row line is at a high voltage (for example, 20 V), since the selected one of the outputs 621 through 624 is also at a high voltage. The selected column line is also at a high voltage and the memory sense program lines are at 0 V. Thus, the gate of the memory cell transistor is at 0 V, and the drain is at a high voltage (for example, 20 V). At this time, the Fowler-Nordheim tunneling is caused to discharge electrons from the floating gate to the drain, and inject holes from the drain into the floating gate, so that the threshold voltage of the memory cell transistor is reduced to, for example, -3 V to 0 V.
It is also known that in order to improve the reliability of data in the above semiconductor memory device, one of the input/output terminals 508 through 516, for example, in FIG. 13 is used for a parity bit by which the presence or absence of error in the information stored in the memory cells can be detected.
The circuit function of the conventional EEPROM has been described as above. The Fowler-Nordheim tunnel current used for writing the memory cell is proportional to the electric field applied across the insulating film (see document 2). The threshold value of the memory cell transistor is changed linearly with the high voltage in the erase or program mode (see document 2). In the conventional EEPROM, only one high voltage value is used in each of the erase mode and program mode and hence in the read mode, only a binary value of a high or low value is detected.